There are a variety of systems for transmitting data between a transmitter and a receiver. Most systems provide a return communications channel by which signals are sent from the receiver back to the transmitter only by using additional signal lines. This is especially true for high-speed digital communication links. However, the additional signal line and its associated interface add significant complication to the communications link.
Other systems provide a return communications channel by adding a second transmitter and a second receiver connected with a second signal line. However, this approach essentially doubles the hardware requirements making such a solution expensive and sometimes even impractical. Furthermore, such duplication becomes a large overhead in the case of an asymmetric communications link, for example, when the bandwidth of the return channel is smaller than that of forward channel.
U.S. Pat. No. 5,675,584 (the “'584 patent”), entitled “High Speed Serial Link for Fully Duplexed Communication,” describes a system for concurrently providing outgoing serial data to, and receiving incoming serial data from, a transmission line using a bidirectional buffer. The disclosed bidirectional buffer receives a mixed data signal on the transmission line. The mixed data signal is a superposition of the outgoing serial data signal and the incoming serial data signal. The incoming serial data signal is extracted from the mixed data signal on the transmission line by subtracting the outgoing serial data signal from the mixed data signal.
The typical bidirectional buffer or bridge circuit includes a differential amplifier which amplifies the difference between the outgoing serial data signal and the mixed data signal on the transmission line. Thus, one input, e.g., the positive input vp, of the differential amplifier is vout+Vin, where vout is the voltage proportional to the output serial data signal, and vin is the voltage proportional to input serial data signal. The second input, e.g., the negative input vn, of the differential amplifier, is vout. The input sensitivity of a bidirectional bridge circuit is limited by the common mode rejection of the differential amplifier. The outgoing data signal is a common mode signal to the differential amplifier. The common mode signal for the differential amplifier can be expressed as follows:vc=(vp+vn)/2=(2vout+vin)/2=vout+vin/2where vc is the common mode input voltage; vp is the positive input voltage; vn is the negative input voltage; vout is the voltage proportional to the output serial data signal; and vin is the voltage proportional to input serial data signal.
If the voltage proportional to the input serial data signal, Vin, is relatively small and the differential amplifier is not ideal, the common mode input of the differential amplifier can control the output of the differential amplifier and the bidirectional bridge circuit can produce an output signal proportional only to the outgoing serial data signal.
The voltage that is proportional to the input data signal can be small when transmission over the transmission line attenuates the incoming serial data signal. This attenuation provides a guideline for common mode and differential gain of the differential amplifier. The common mode rejection ratio of the differential amplifier should be larger than the attenuation by the transmission line. This guideline is expressed as follows:AC·(vout+vin/2)<Ad·vin=Ad·Γ·vout,where AC is the common mode gain of the differential amplifier: Ad is the differential gain of the differential amplifier; and
  Γ  =            v      in              v      out      is the attenuation coefficient of the transmission line. Therefore, meeting the condition
            A      d        /          A      C        >      (                  Γ                  -          1                    +              1        2              )  provides improved operation of a bidirectional link.
Furthermore, the difference in the loading condition between the two input nodes of the differential amplifier affects the performance of the bridge circuit differential amplifier. This asymmetry comes from the fact that one of the input nodes of the differential amplifiers couples to the pad and transmission line while the other input node does not. The extra loading due to the protection device against electrostatic discharge and parasitic devices associated with the pad can have an adverse effect on the switching transients of the differential amplifier.
In the figures, the same reference numbers identify identical or substantially similar elements or acts. Figure numbers followed by the letters “A,” “B,” etc. indicate that two or more figures represent alternative embodiments or methods under aspects of the invention.
As is conventional in the field of electrical circuit representation, sizes of electrical components are not drawn to scale, and various components can be enlarged or reduced to improve drawing legibility. Component details have been abstracted in the figures to exclude details such as position of components and certain precise connections between such components when such details are unnecessary to the invention.
The headings provided herein are for convenience only and do not necessarily affect the scope or meaning of the claimed invention.